1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method to read flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices to reduce stress on non-selected cells during read.
2. Discussion of the Related Art
A microelectronic Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting select transistors that would enable the cells to be erased independently. As a result all of the cells must be erased simultaneously as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary "1" or "0" or to erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together to a common source. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying typically 8-9 volts to the control gate, approximately 5 volts to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
The cell is read by applying typically 5 volts to the control gate, 1-2 volts to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (.apprxeq.4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (.apprxeq.2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying typically 12 volts to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can erase a cell.
FIG. 2 is a graph showing the change in the erase threshold voltage (Erase V.sub.t) with the number of erase/program cycles. The cycling phenomenon is caused by the generation of hot-hole pairs resulting from band-to-band tunneling. Whereas Fowler-Nordheim tunneling from the floating gate through the tunnel oxide layer to the source results in erasure of a cell, band-to-band tunneling also occurs between the substrate and the source. When a positive voltage is applied to the source junction with the control gate negative, a deep depletion region is formed underneath the gate-to-source overlap region. The tunneling of valence band electrons into the conduction band generates electron-hole pairs. The source junction collects the electrons and the holes are collected by the substrate.
Since the minority carriers (holes) generated thermally or by band-to-band tunneling in the source region flow to the substrate due to the lateral field near the Si--SiO.sub.2 interface, the deep depletion region remains present and the band-to-band tunneling can continue without creating an inversion layer. The generated holes gain energy because of the electric field in the depletion region. While the majority of these generated holes flow into the substrate, some of them gain sufficient energy to surmount the Si--SiO.sub.2 barrier and are trapped in the tunnel oxide layer. This stress to the tunnel oxide layer in a particular bit is a cumulative effect and as shown in FIG. 2 the erase V.sub.t approaches the program V.sub.t. As the erase V.sub.t approaches the program V.sub.t increasing numbers of electrons can flow into the floating gate whether or not the bit is programmed or erased. This phenomenon is termed bit charge gain and the floating gate can be eventually charged during a number of read operations causing the bit to change from an erased bit to a programmed bit. The dashed line 200 represents the critical value of the erase V.sub.t and indicates that when the erase V.sub.t approaches the region indicated by the dashed line 200 the device either fails or will fail soon. In the conventional method of reading a flash memory device, the relatively large voltage differential applied to all of the cells on the wordline on which the cell being read is located causes a relatively large bit charge gain. This means that all of the cells on the wordline are affected by stress whether or not they are being read and that each read operation can add to the transfer of electrons to each floating gate on the wordline on which the bit being read is attached. In order to decrease the bit charge gain and to extend the number of cycles before the device fails it would be advantageous to read the device with lower differential read voltages.
Therefore, what is needed is a method to read the flash memory device without unduly adding charge to the floating gate of cells being read and decreasing bit charge gain of the cells not being read.